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Department  Electrical and Electronics Engineering
Year 2nd year
Semester 3rd Semester
University Anna University
Regulation  R2017
Subject Code EE8351
Subject Name DIGITAL LOGIC CIRCUITS
Download File EE8351 DIGITAL LOGIC CIRCUITS Lecture Notes, Books, Important 2 Marks Question and Answers, 16 Mark Question with Answers, Syllabus & Question Bank

 

 

EE8351 DIGITAL LOGIC CIRCUITS Syllabus

UNIT I NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES
Review of number systems, binary codes, error detection and correction codes (Parity and Hamming code) – Digital Logic Families -comparison of RTL, DTL, TTL, ECL and MOS families -operation, characteristics of digital logic family.

UNIT II COMBINATIONAL CIRCUITS
Combinational logic – representation of logic functions-SOP and POS forms, K-map representations – minimization using K maps – simplification and implementation of combinational logic – multiplexers and de multiplexers – code converters, adders, subtractors, Encoders and Decoders.

UNIT III SYNCHRONOUS SEQUENTIAL CIRCUITS
Sequential logic- SR, JK, D and T flip flops – level triggering and edge triggering – counters – asynchronous and synchronous type – Modulo counters – Shift registers – design of synchronous sequential circuits – Moore and Melay models- Counters, state diagram; state reduction; state assignment.

UNIT IV ASYNCHRONOUS SEQUENTIAL CIRCUITS AND PROGRAMMABILITY LOGIC DEVICES
Asynchronous sequential logic circuits-Transition tability, flow tability-race conditions, hazards &errors in digital circuits; analysis of asynchronous sequential logic circuits- introduction to Programmability Logic Devices: PROM – PLA –PAL, CPLD-FPGA.

UNIT V VHDL
RTL Design – combinational logic – Sequential circuit – Operators – Introduction to Packages – Subprograms – Test bench. (Simulation /Tutorial Examples: adders, counters, flip flops, Multiplexers & De multiplexers).

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